BTEC Level 5 Unit 37 Architecture (K/618/7456) Assignment Brief 2026

Unit 37 Architecture Assignment Brief 2026

Qualification Pearson BTEC Level 5 Higher Nationals in Computing
Unit Number 37
Unit Title Architecture
Unit code K/618/7456
Unit type Optional
Unit level 5
Credit value 15

Introduction

Computer architecture engineers work in industries such as telecoms, automotive and aerospace and the aim of this unit is to give students knowledge of computer systems, functionality and organisation. Students will examine systems architecture and elements of computing machines and the principles and fundamentals of how computer systems work.

The unit introduces students to the hardware and software architecture of computer systems and low-level language program development using CPU registers to manipulate data. They will explore how program instructions and data types can be represented, stored in a computer system and used to carry out a computing task.

Among the topics included in this unit are: computer architecture elements, CPU instruction sets, fetch-execute cycle, CPU registers, binary calculations, use of PC and stack, reading/writing to peripherals, architectural security aspects, including protected memory segmentation and synchronous/asynchronous channel I/O operations, parallel machines, emerging computer architectures and security considerations.

Students will develop skills such as communication literacy, critical thinking, analysis, reasoning and interpretation, which are crucial for gaining employment and developing academic competence.

Learning Outcomes

By the end of the unit students will be able to:

LO1 Examine the functions of computer system components

LO2 Discuss how data and programs can be represented within computer systems

LO3 Demonstrate the principles of processor operations

LO4 Investigate advanced computer architectures and performance.

Essential Content

LO1 Examine the functions of computer system components

Component functions:

Logical/physical component functions; clock synchronization, processor (CPU), buses, memory maps and interrupt request (IRQ), Boolean logic gates, adder circuits, analysis of how components interact to carry out the fetch-execute cycle and modify data, definition and use of CPU registers. I/O device memory.

LO2 Discuss how data and programs can be represented within computer systems

Data/program representation:

Program/data representation and storage; description, use and storage of data types integer, decimal and character, absolute/relative program location, firmware/software.

LO3 Demonstrate the principles of processor operations

Principles of processor operations:

Low-level program instruction sets, RISC, development of assembler programs (including at least one JMP instruction) to manipulate stored data using CPU registers; I/O memory and IRQ locations.

LO4 Investigate advanced computer architectures and performance

Advanced architectures:

Multiple instruction, multiple data (MIMD) parallelism (Flynn’s Taxonomy), cache, instruction/graphics pipelining, unconventional architectures, benchmarking, functional unit mix, IRQ latency.

Learning Outcomes and Assessment Criteria

Pass Merit Distinction
LO1 Examine the functions of computer system components  

 

D1 Evaluate through illustration how the processor is physically connected to memory and input/output (I/O) devices using the system buses.
P1 Investigate the key computer system components and how they interact.

P2 Show how the different types of memory can be attached to a processor.

M1 Compare the roles played by different types of memory.
LO2 Discuss how data and programs can be represented within computer systems  

 

D2 Evaluate how locating a program absolutely in memory can aid ICE target system debugging.
P3 Investigate, using examples, how different types of data can be converted and stored in computer systems.

P4 Carry out Boolean logic operations.

 M2 Show how, using examples, floating point numbers can be represented in binary form.

M3 Illustrate how adder circuits are used to add binary numbers.
Pass Merit Distinction
LO3 Demonstrate the principles of processor operations  

 

D3 Examine how the width of the data bus and address bus affect processor performance and complexity.
P5 Illustrate the use of the different processor registers in the fetch-execute cycle.

P6 Illustrate, with an example, how polling and interrupts are used to allow communication between processor and peripherals.

 M4 Create a low-level program that includes decision making, branching and I/O operations.

M5 Investigate the function of an interrupt handler.
LO4 Investigate advanced computer architectures and performance  

 

D4 Critically evaluate, with illustrations, computer performance improvements with MIMD architectures.
P7 State the function of DirectX API, describing its advantages and disadvantages. M6 Assess how instruction pipelining modifies the performance of a computer system.

M7 Evaluate how the DirectX API is used by application programmers to control graphics functions.

Recommended Resources

Textbooks

Adamatzky, A. (2013) Collision-Based Computing. Springer.

Blum, R. (2005) Professional Assembly Language Programming. John Wiley & Sons.

Gaura, E., Hibbs, D. and Newman, R. (2008) Computer Systems Architecture. Lexden.

Links

This unit links to the following related units:

Unit 9: Computer Systems Architecture

Unit 40: Client/Server Computing Systems.

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