This guide covers BTEC Higher Nationals in Engineering Unit 84 Semiconductor Manufacture, a Level 4, 15-credit unit from the Semiconductor Technologies pathway, which now appears in the current Higher Nationals as Unit 4039 Semiconductor Manufacture (L/651/0768). It explains each learning outcome and every Pass, Merit and Distinction criterion, then gives you a report structure, short model-answer extracts, a worked yield calculation and the mistakes that cost marks.
Assignment brief: Unit 4039 Semiconductor Manufacture Assignment Brief — read the full task first, then use this guide to plan and check your answer.
What the Unit 84 Semiconductor Manufacture assignment asks you to do
The unit follows a chip from raw silicon to a packaged, tested integrated circuit. Your assignment asks you to show that you understand four things: the automated equipment a fab runs on, how a silicon wafer is made ready for processing, how that wafer is turned into finished ICs, and how inspection and test data are used to raise yield. Most centres collect the evidence as a technical report.
The criteria in the Unit 4039 brief are written around a generic automated fabrication plant rather than a named company. Choose one technical example, such as a 300 mm CMOS logic line, and use it consistently. If your centre still uses the Unit 84 title, the scope is the same; check the wording on your own brief.
This unit is about making devices. If your assignment is about how devices behave in circuits and how integrated circuits are designed, you need the companion guide for Unit 87 Semiconductor Integrated Electronics instead.
Learning outcomes for Unit 84 / Unit 4039 Semiconductor Manufacture
| Learning outcome | What it covers |
|---|---|
| LO1 | Operational characteristics, selection criteria and application of equipment used in automated systems for fabricating semiconductor devices. |
| LO2 | The individual process stages in producing a semiconductor wafer suitable for further processing in an automated fab. |
| LO3 | The processes needed to take a wafer and produce a finished integrated circuit. |
| LO4 | How inspection and test data collected during manufacture are used to improve the yield of each IC through to final packaging. |
Pass, Merit and Distinction criteria explained
The codes below follow the Unit 4039 brief. Check the exact wording on the brief your tutor issued.
| Criterion | What it asks | How to evidence it |
|---|---|---|
| P1 | Describe the operational characteristics of the system for fabricating devices on a wafer. | Explain how the main tool groups work (lithography, etch, deposition, implant, thermal, CMP, metrology) and how wafers move between them. |
| P2 | Explain the difference in structure between how a BJT and a MOSFET are made. | Labelled cross-sections of each device plus the process steps that create each region. |
| M1 | Explore selection criteria and application of fabrication equipment. | Compare tools against throughput, resolution, uniformity, contamination and cost of ownership, with a reason for each choice. |
| D1 | Analyse the system characteristics of a fabrication facility. | Treat the fab as a system: cleanroom, utilities, automated material handling, manufacturing execution system, cycle time and bottlenecks. |
| P3 | Describe different methods of producing a silicon ingot. | Czochralski and float zone growth, with purity, oxygen content and diameter compared. |
| M2 | Discuss the need to control the environment around wafer production. | Particles, temperature, humidity, vibration, chemical and molecular contamination, electrostatic discharge, and their effect on yield. |
| D2 | Evaluate the methods used to prepare a wafer for fabrication. | Judge slicing, lapping, etching, polishing and cleaning options on damage, flatness, cost and suitability. |
| P4 | Explain the stages of front-end and back-end wafer fabrication. | A process flow from bare wafer to transistors (front end) and on to interconnect, or to assembly and test, depending on your brief’s definition. |
| M3 | Explore methods used to connect the chip to the printed wiring board. | Wire bonding, flip-chip and the package-to-board step (through-hole, surface mount, BGA). |
| D3 | Evaluate wafer testing methods used during manufacture. | Parametric test, wafer probe, burn-in and final test weighed for cost, coverage and timing. |
| P5 | Describe how data is collected during manufacture. | In-line metrology, defect inspection, tool sensor data and electrical test, and where each sits in the flow. |
| P6 | Investigate inspection and testing techniques used to improve processes. | Optical and e-beam inspection, SEM review, CD measurement, film thickness and sheet resistance measurement. |
| M4 | Identify the principal types of faults and defects. | Classify defects (particles, pattern, crystal, film, electrical) and link each to a likely cause. |
| D4 | Analyse how process data is used to improve overall yield. | Use a yield model, wafer maps and statistical process control to show cause and effect, ideally with numbers. |
How to answer LO1: fabrication equipment and the fab as a system
For P1, describe what each tool group does to the wafer; for M1, add why one tool is chosen over another; for D1, analyse the whole facility.
- Lithography: deep ultraviolet scanners (248 nm and 193 nm, including 193 nm immersion) and extreme ultraviolet at 13.5 nm for the smallest features; key parameters are resolution, overlay accuracy and wafers per hour.
- Etch: wet etching is isotropic and cheap; plasma or reactive ion etching is anisotropic and gives vertical sidewalls.
- Deposition: CVD and PECVD for dielectrics, PVD (sputtering) for metals, atomic layer deposition for very thin, conformal films.
- Doping and thermal: ion implanters set dose and depth precisely; furnaces and rapid thermal processing grow oxides and activate dopants.
- CMP and metrology: chemical mechanical planarisation flattens layers; metrology tools check thickness, critical dimension and overlay.
- Automation: wafers travel in sealed carriers (FOUPs on 300 mm lines) on an automated material handling system, scheduled by a manufacturing execution system.
Example paragraph: For the gate-patterning layer the line uses a 193 nm immersion scanner rather than a dry 193 nm tool. Immersion places water between the final lens and the wafer, raising the numerical aperture above 1 and allowing a smaller printed feature. The trade-off is cost and a risk of water-mark defects, so it is kept for critical layers, while non-critical implant masks run on cheaper, higher-throughput 248 nm tools.
For D1, analyse links rather than list tools: lithography is usually the bottleneck, so its uptime sets fab output; long re-entrant flows (the wafer returns to the same tool groups many times) lengthen cycle time; and a failure in ultrapure water or gas supply stops every tool at once.
P2: BJT versus MOSFET structure
Draw both cross-sections. A planar npn BJT is a vertical device: an n+ buried layer, an n-type epitaxial collector, a p-type base and an n+ emitter, with current flowing down through the layers, so base width and doping profiles are critical and isolation between transistors is needed. A MOSFET is a lateral device: a thin gate oxide, a polysilicon or metal gate, and source and drain implanted on each side of the gate (self-aligned), with current flowing along the surface channel, so gate oxide quality and gate length control matter most.
How to answer LO2: from ingot to prepared wafer
Structure this section as a process flow, then compare and judge.
- Crystal growth (P3): Czochralski (CZ) pulls a seed crystal from a melt in a quartz crucible; it scales to 300 mm but picks up oxygen from the crucible. Float zone (FZ) passes a molten zone along a polysilicon rod with no crucible, giving higher purity and lower oxygen, but at smaller diameters.
- Shaping: grinding to diameter, adding a notch or flat for orientation.
- Slicing, edge rounding, lapping or grinding, etching to remove saw damage, polishing to a mirror finish, and final cleaning.
- Optional epitaxial layer growth.
Example paragraph: Multi-wire sawing has replaced the inner-diameter saw for large wafers because it cuts hundreds of wafers at once with lower kerf loss. It still leaves a damaged surface layer, so the wafers are lapped or ground and then chemically etched before polishing. Skipping the etch would save a step but leave sub-surface cracks that can propagate during later thermal cycles, so on balance the extra stage is justified by fewer breakages and better flatness for lithography.
For M2, explain why each environmental control exists: a particle larger than a fraction of the feature size can kill a die; temperature drift affects lithography overlay; humidity affects resist behaviour; vibration blurs exposure; metal ions shift threshold voltages. Mention cleanroom classes under ISO 14644-1. For D2, give a judgement, not just a description.
How to answer LO3: wafer to finished integrated circuit
A typical CMOS flow for P4:
- Front end of line: isolation (shallow trench isolation), well implants, gate oxide growth, gate deposition and patterning, source/drain implants, anneal, silicide.
- Back end of line: pre-metal dielectric, contacts, metal layers (often copper damascene with CMP), vias, passivation.
- Assembly and test (called “back end” in many companies): wafer probe, thinning, dicing, die attach, bonding, encapsulation, final test.
Say which meaning of front end and back end you are using; both appear in industry and assessors credit students who define their terms.
For M3, compare chip-to-package and package-to-board methods: gold or copper wire bonding (cheap, flexible, longer leads), flip-chip with solder bumps (short paths, better electrical performance, needs underfill), and board mounting by through-hole or surface mount, including ball grid arrays.
Example paragraph: Wafer probe is carried out before dicing so that failing die are inked or mapped and never packaged, which avoids paying assembly costs on scrap. However, probe cannot fully test high-speed or thermal performance, so a final test after packaging remains necessary. Burn-in screens early-life failures but adds time and cost, so it is usually reserved for automotive or high-reliability products. The most cost-effective plan therefore combines thorough probe, selective burn-in and a final test aimed at package-related faults.
How to answer LO4: data, defects and yield
- P5: data sources are in-line metrology (film thickness, critical dimension, overlay), defect inspection after key layers, tool sensor logs, parametric test on scribe-line structures and wafer probe results.
- P6: bright-field and dark-field optical inspection, SEM defect review, CD-SEM, ellipsometry for film thickness, four-point probe for sheet resistance.
- M4: classify defects as particles, scratches, pattern defects (bridging, opens), overlay errors, crystal defects, voids in metal and gate oxide breakdown, each with a likely cause.
- D4: show how wafer maps, Pareto charts, control charts and a yield model lead to a corrective action.
Worked example: die per wafer and defect-limited yield
A fab makes a 10 mm × 10 mm die (area A = 100 mm² = 1 cm²) on 300 mm wafers. Estimate good die per wafer, then show the effect of a defect-reduction project.
Step 1: gross die per wafer. A common estimate is DPW = πr²/A − πd/√(2A).
- πr²/A = π × 150² / 100 = 70,686 / 100 = 706.9
- πd/√(2A) = π × 300 / √200 = 942.5 / 14.14 = 66.6
- DPW = 706.9 − 66.6 ≈ 640 gross die
Step 2: die yield. Using the Poisson model Y = e−D₀A with a defect density D₀ = 0.5 defects/cm²: Y = e−0.5 × 1 = 0.607, so about 60.7%. Good die = 640 × 0.607 ≈ 388.
Step 3: after improvement. Inspection data show most killer defects are particles from one etch chamber. After a chamber clean schedule change, D₀ falls to 0.3 defects/cm². Y = e−0.3 = 0.741, so good die = 640 × 0.741 ≈ 474, an increase of about 86 good die per wafer.
Step 4: overall yield. Combine stages: wafer (line) yield 0.98 × die yield 0.607 × assembly yield 0.99 × final test yield 0.97 = 0.571, or 57.1% overall. The Poisson model assumes randomly scattered defects; clustered defects are better described by models such as the negative binomial, which is a good point to raise for Distinction.
Common mistakes that cost marks
- Listing equipment names without explaining how each tool works or why it is chosen, which caps you at P1.
- Drawing BJT and MOSFET symbols instead of physical cross-sections for P2.
- Describing CZ and FZ growth without comparing oxygen content, purity and diameter.
- Mixing the two meanings of front end and back end without defining them.
- Describing data collection for LO4 but never showing how a number changed a decision.
How to move from Merit to Distinction
The four D criteria use “analyse” and “evaluate”. For D1, explain cause and effect inside the fab: bottleneck tools, cycle time, utility dependence, automation and cost. For D2 and D3, weigh at least two methods against stated criteria and finish with a justified recommendation. For D4, use real or realistic numbers, such as the yield calculation above or a wafer map showing an edge-ring failure pattern, and trace them to a root cause and a measured improvement. A short limitations paragraph shows critical thinking.
FAQs
Is Unit 84 Semiconductor Manufacture the same as Unit 4039?
Unit 4039 is the current Higher Nationals version of Semiconductor Manufacture and covers the same four areas: equipment, wafer preparation, IC fabrication and yield. Always follow the criteria printed on the brief your centre gives you.
Do I need calculations in this unit?
They are not always required, but numbers make LO4 much stronger. A die-per-wafer and yield calculation, or a control chart with limits, gives clear evidence for D4.
What is the difference between wafer probe and final test?
Wafer probe tests each die electrically before dicing so faulty die are not packaged. Final test checks the packaged device, catching assembly faults and testing performance at speed and temperature.
Why is Czochralski growth used for most wafers if float zone is purer?
Czochralski scales to 300 mm diameter at lower cost. Float zone is kept for products such as power devices where low oxygen and high resistivity matter.
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If you are short of time or stuck on the yield section, you can get expert help with your BTEC assignment. For wider HNC and HND support, see our guides to the HND in Electrical and Electronic Engineering and the Level 5 HND in Engineering.
