This guide covers BTEC Higher Nationals in Engineering Unit 87 Semiconductor Integrated Electronics, a Level 5, 15-credit specialist unit from the Semiconductor Technologies pathway of the HND. It explains what the assignment usually asks for, how to structure each part of your report, and what Pass, Merit and Distinction work looks like, with model paragraphs and a worked MOSFET and CMOS power calculation.
Related brief: Unit 4039 Semiconductor Manufacture Assignment Brief — this is the Level 4 manufacturing unit from the same pathway, not the Unit 87 brief. Use it for background on how the devices you analyse here are made.
What the Unit 87 Semiconductor Integrated Electronics assignment asks you to do
Unit 87 sits at Level 5 and builds on the Level 4 manufacturing units. Where Unit 84 Semiconductor Manufacture asks how a chip is made, Unit 87 asks how semiconductor devices behave and how they are combined into integrated circuits for real applications. You move from the physics of a doped junction to transistor characteristics, then to analogue and digital IC building blocks and the trade-offs a designer makes between speed, power, area and cost.
Briefs for this unit are written by each centre, so the scenario varies. A common format is a technical report for an electronics company: explain the devices, measure or simulate their characteristics, design or analyse a small integrated circuit block, and recommend an IC approach for an application. Some centres add a practical or simulation log (for example in LTspice) and a short reflection.
Typical topic areas in Unit 87
We have not been able to confirm the official learning outcome wording for this unit, so the table below groups the content that Unit 87 assignments typically assess. Map it against the learning outcomes printed on your own brief.
| Topic area | What it covers |
|---|---|
| Semiconductor physics | Energy bands, intrinsic and extrinsic silicon, n-type and p-type doping, carrier drift and diffusion, the pn junction and depletion region. |
| Device structure and characteristics | Diodes, BJTs and MOSFETs: I-V curves, operating regions, threshold voltage, transconductance, leakage, temperature effects. |
| Integrated circuit building blocks | CMOS inverter and logic gates, current mirrors, differential pairs, op-amp stages, memory cells, mixed-signal blocks such as ADCs. |
| Design, simulation and layout | SPICE models, schematic simulation, design rules, parasitic capacitance and resistance, matching. |
| Applications and technology choice | Analogue, digital, mixed-signal and power ICs; ASIC versus FPGA versus standard parts; scaling, power and reliability. |
Pass, Merit and Distinction criteria explained
HND units use Pass criteria that describe or explain, Merit criteria that analyse or compare, and Distinction criteria that critically evaluate and justify. Check the exact P, M and D wording on your brief; the table shows what each level usually looks like in this unit.
| Grade level | What it asks | How to evidence it |
|---|---|---|
| Pass | Describe or explain device physics, structures and characteristics accurately. | Labelled diagrams, correct equations with units, I-V graphs from data sheets, lab work or simulation. |
| Merit | Analyse device or circuit behaviour and compare options. | Calculate parameters from your results, compare BJT and MOSFET or two IC approaches against stated criteria. |
| Distinction | Critically evaluate performance and justify a design or technology choice. | Discuss limitations of models and measurements, trade-offs and a recommendation backed by numbers. |
How to answer the device physics section
Start from the material. Explain why silicon is a semiconductor (a band gap of about 1.12 eV at room temperature), how doping with phosphorus (donor) or boron (acceptor) creates n-type and p-type material, and how a pn junction forms a depletion region with a built-in potential. Then link this to device behaviour: forward bias narrows the depletion region and current rises exponentially; reverse bias leaves only a small leakage current until breakdown.
- Use an energy-band diagram and a junction diagram.
- Quote the diode equation I = IS(eV/(nVT) − 1) and explain each term.
- Explain the effect of temperature on leakage and forward voltage.
Example paragraph: Increasing the doping on both sides of the junction narrows the depletion region, which raises junction capacitance and lowers reverse breakdown voltage. This is why a fast switching diode and a high-voltage rectifier are built differently: the first uses heavy doping and a small area to keep transit time short, while the second uses a lightly doped drift region to spread the electric field. A designer selecting a diode for a 400 V supply therefore accepts slower recovery in exchange for safe blocking voltage.
How to answer the transistor characteristics section
Show both device types and how their characteristics are obtained, either measured on a curve tracer, taken from a data sheet or simulated.
- BJT: input and output characteristics, active, saturation and cut-off regions, current gain β, the Early effect.
- MOSFET: transfer and output curves, threshold voltage, linear and saturation regions, transconductance gm, channel-length modulation, subthreshold leakage.
- Compare: BJTs offer high gm per unit current and good matching for analogue work; MOSFETs need almost no gate current and pack densely, which is why CMOS dominates digital ICs.
Example paragraph: The simulated NMOS output curves flatten above VDS ≈ VGS − VT, confirming the move into saturation, but they are not perfectly flat. The slight upward slope is channel-length modulation, and it was larger for the 0.18 µm device than the 1 µm device. For an amplifier stage this lowers output resistance and therefore gain, so the longer device would be chosen for the gain stage despite its larger area.
How to answer the integrated circuit design section
This is where Unit 87 earns its name. Pick one or two building blocks and analyse them properly rather than describing ten briefly.
- A CMOS inverter: voltage transfer characteristic, noise margins, propagation delay, static and dynamic power.
- A current mirror or differential pair: matching, output resistance, why layout symmetry matters.
- Show the simulation set-up (models, supply, load) and your results, then interpret them.
- Note how parasitic capacitance from interconnect, which you meet in Unit 84, limits speed.
How to answer the applications and technology choice section
Choose a realistic product (for example a battery sensor node or a motor controller) and decide how to implement the electronics: a standard microcontroller plus discrete parts, an FPGA, a mixed-signal ASIC, or a system-on-chip. Judge each against unit cost, volume, development cost and time, power, size and risk.
Example paragraph: For a wearable sensor expected to sell 2 million units, a mixed-signal ASIC combining the analogue front end, ADC and a low-power processor is justified. The one-off design and mask costs are high, but they are spread across a large volume, and integration cuts board area and standby current. For a 500-unit industrial tester the same costs could not be recovered, so an FPGA with an external ADC is the better choice even though each unit costs more.
Worked example: MOSFET drain current and CMOS dynamic power
Part 1: drain current in saturation. An NMOS transistor has μnCox = 200 µA/V², W/L = 10, VT = 0.5 V and VGS = 1.8 V. Ignoring channel-length modulation:
- ID = ½ μnCox (W/L)(VGS − VT)²
- ID = 0.5 × 200 × 10⁻⁶ × 10 × (1.8 − 0.5)²
- ID = 1 × 10⁻³ × 1.69 = 1.69 mA
Transconductance gm = 2ID/(VGS − VT) = 2 × 1.69 mA / 1.3 V = 2.6 mA/V.
Part 2: dynamic power of a CMOS block. A digital block has a total switched capacitance C = 1 nF, an activity factor α = 0.1, a clock of f = 1 GHz and a supply VDD = 1.2 V.
- P = αCVDD²f = 0.1 × 1 × 10⁻⁹ × 1.2² × 1 × 10⁹
- P = 0.1 × 1.44 = 0.144 W (144 mW)
Part 3: effect of lowering the supply. At VDD = 1.0 V, P = 0.1 × 1 × 10⁻⁹ × 1.0² × 1 × 10⁹ = 0.100 W, a reduction of (144 − 100)/144 ≈ 30.6%. Because power depends on VDD², a small voltage cut gives a large saving, but lower supply also reduces VGS − VT, so drive current and speed fall. Discussing that trade-off, and the rising share of leakage power in small geometries, is the kind of evaluation that supports a Distinction.
Common mistakes that cost marks
- Writing a manufacturing report: fabrication detail belongs in Unit 84, while Unit 87 needs device and circuit behaviour.
- Copying data-sheet graphs without reading values from them or explaining what they show.
- Using the saturation equation for a MOSFET that is actually in the linear region.
- Presenting simulation screenshots with no set-up details, units or interpretation.
- Comparing BJT and MOSFET with vague words (“better”, “faster”) instead of parameters.
- Recommending an IC approach without considering volume, cost and development time.
How to move from Merit to Distinction
Merit work analyses; Distinction work judges. Compare your calculated or simulated results with measured or data-sheet values and explain any differences (model simplifications, temperature, process variation). State the limits of the square-law model in short-channel devices. Finish each major section with a justified recommendation, and support it with numbers such as current, gain, delay or power figures. A short reflection on how you would improve the test or simulation also helps.
FAQs
What is the difference between Unit 84 and Unit 87?
Unit 84 Semiconductor Manufacture (Level 4) covers fabrication equipment, wafer processing and yield. Unit 87 Semiconductor Integrated Electronics (Level 5) covers how devices behave and how they are combined into analogue, digital and mixed-signal integrated circuits.
Which software can I use for the simulation tasks?
Any SPICE-based simulator is suitable; LTspice is free and widely used in colleges. Use the transistor models your centre provides and record the model names and settings in your report.
Do I need to design a full integrated circuit?
No. Assessors expect you to analyse building blocks such as an inverter, a current mirror or an amplifier stage in depth. Full chip layout is beyond the scope of a 15-credit unit.
Why does CMOS dominate digital ICs?
A CMOS gate draws almost no current when it is not switching, MOSFETs need no steady gate current, and they scale to very small sizes. That gives low power and high density, although leakage becomes significant in small geometries.
How should I reference equations and data sheets?
Use the referencing style your centre requires, usually Harvard. Cite manufacturer data sheets and textbooks for equations and parameter values.
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If the device analysis or simulation is holding you up, you can get expert help with your BTEC assignment. You may also find our guide to the HND in Electrical and Electronic Engineering useful for related units.
